1. Field of the Invention
This invention generally relates to a recording apparatus, a reproducing apparatus, and a recording medium. This invention particularly relates to a recording apparatus implementing modulation suited for the recording of a signal of a run-length-limited code on a recording medium such as an optical disc. In addition, this invention particularly relates to a reproducing apparatus for recovering original information code words from a signal of a run-length-limited code which is reproduced from a recording medium such as an optical disc.
Furthermore, this invention particularly relates to a recording medium for storing a signal of a run-length-limited code.
2. Description of the Related Art
Turbo codes are in a class of high-performance error correction codes, and come closest to approaching the Shannon limit, that is, the theoretical limit of maximum information transfer over a noisy channel. The turbo codes make it possible to increase an available bandwidth without increasing the power of a transmission. Signals of the turbo codes have payload data and parity bits for the payload data. The main drawback of the turbo codes is a relatively high latency.
Hongwei Song, Jingfeng Liu, and B. V. K. Vijaya Kumar have reported “DC-Free (d, k) Constrained Low Density Parity Check (LDPC) Codes”, Technical Digest 2002 IEEE, ThA.4, pages 377-379. According to the report, a DC-free (1, 7) RLL LDPC code is constructed for low signal-to-noise ratio and high-density recording of data on a recording medium. Specifically, the DC-free (1, 7) RLL LDPC code is generated as follows. The user information bits are first passed through a conventional (1, 7) RLL encoder, and the resultant (1, 7) RLL coded sequence goes through a conventional LDPC encoder. Since the LDPC encoder can be easily made systematic, the information bit part of the LDPC code word satisfies (1, 7) RLL. The resultant LDPC coded sequence is encoded by an extended bit insertion encoder. The extended bit insertion encoder multiplexes the parity check bits with the information bits. Specifically, the extended bit insertion encoder groups the parity check bits into two bits per group and inserts them periodically into the information bits which already satisfy (1, 7) RLL. In more detail, the extended bit insertion encoder groups the parity check bits as two bits P1 and P2 in one group and places a control bit B between the two parity check bits P1 and P2 to make sure that they do not violate “1” run length constraint. If both of the parity check bits P1 and P2 are “0”, then the control bit Bis set to “1”. Otherwise, the control bit B is set to “0”. Furthermore, the extended bit insertion encoder generates two control bits A1 and A2 placed immediately before each parity check and control bit set “P1-B-P2”, and two control bits A3 and A4 placed immediately after the bit set “P1-B-P2”. The control bits A1 and A4 are used primarily to ensure that (1, 7) RLL will not be violated. The control bits A2 and A3 are used to control the DC component. There is a straightforward method to control the DC component by selecting the value of the control bits A2 and A3 to control the value of the running digital sum (RDS). In the bit stream outputted from the extended bit insertion encoder, the number ratio of the parity bits to the information bits is relatively high. Thus, the effective encoding rate is relatively low. Specifically, every two parity check bits P1 and P2 are extended into a 7-bit set “A1-A2-P1-B-P2-A3-A4”, and hence the bit number is increased by a factor of 7/2.
Generally, LDPC codes are excellent in decoding performance and block error rate. Like turbo codes and RA (repeat and accumulate) codes, LDPC codes provide a near-Shannon capacity performance when the code length is great. In addition, LDPC codes hardly cause an error floor phenomenon.
In the case where turbo codes and LDPC codes are used for signals to be recorded on optical discs, it is desirable to subject the turbo-code signals and the LDPC-code signals to run-length limitation and DSV (digital sum variation or digital sum value) control to make them in harmony with the transmission-line characteristics of the optical discs. Generally, it is difficult to directly calculate the desired states of parity bits for turbo-code signals and LDPC-code signals subjected to run-length limitation and DSV control.
U.S. Pat. No. 6,297,753 B1 corresponding to Japanese patent application publication number P2000-286709A discloses a modulation system for encoding every “p”-bit block of digital data into a “q”-bit code word, serially connecting the resultant code words, and thereby converting the digital data into a code-word sequence in the form of a bit stream which observes run length limiting rules such that a minimum zero-run-length and a maximum zero-run-length are equal to 3 T and 11 T respectively. The modulation system in U.S. Pat. No. 6,297,753 B1 includes a plurality of encoding tables for converting “p”-bit input data words into “q”-bit output code words. Each of the encoding tables lists output code words and state-information pieces assigned to input data words. The state-information pieces are designed to select one among the encoding tables which will be accessed for the conversion of a next input data word. Furthermore, the group of encoding tables is designed so that the NRZI modulation results of output code words in specified encoding tables which are assigned to each predetermined input data word are opposite in parity or polarity (“odd-even” in the number of bits of “1”). This design of the encoding tables is utilized in performing DSV control of the output-code-word sequence.
There is a background-art data modulation system implementing both DSV control and LDPC (low density parity check) encoding. The background-art system is not prior art to this invention, and is described in Japanese patent application publication number P2005-78687A corresponding to U.S. patent application Ser. No. 10/885,320 filed on Jul. 7, 2004. The background-art system includes a set of encoding tables, and a first device for modulating “m”-bit input data words into “n”-bit information code words respectively by referring to the encoding tables, where “m” denotes a first predetermined natural number equal to an integer multiple of 4 and “n” denotes a second predetermined natural number equal to an integer multiple of 6, and the number “n” is greater than the number “m”. The encoding tables contain information code words assigned to input data words, and contain table selection information accompanying each information code word. The table selection information designates one among the encoding tables which is used next to generate an information code word immediately following the information code word accompanied with the table selection information. Information code words in first specified one of the encoding tables which are assigned to prescribed input data words are opposite in polarity of DSV to information code words in second specified one of the encoding tables which are assigned to the prescribed input data words.
In the background-art system, a second device generates a final information code word in response to a current input data word different from the prescribed input data words by referring to one of the encoding tables. A third device generates a first candidate information code word in response to a current input data word equal to one of the prescribed input data words by referring to the first specified one of the encoding tables. A fourth device generates a second candidate information code word in response to the current input data word equal to said one of the prescribed input data words by referring to the second specified one of the encoding tables. A fifth device generates a first succession of information code words including the final information code word generated by the second device and the first candidate information code word generated by the third device. A sixth device generates a second succession of information code words including the final information code word generated by the second device and the second candidate information code word generated by the fourth device. A seventh device calculates a first DSV from the first succession of information code words which is generated by the fifth device. An eighth device calculate a second DSV from the second succession of information code words which is generated by the sixth device. A ninth device determines which of an absolute value of the first DSV calculated by the seventh device and an absolute value of the second DSV calculated by the eighth device is smaller. A tenth device selects one from the first succession of information code words and the second succession of information code words which corresponds to the smaller DSV absolute value determined by the ninth device as at least a part of a final information-code-word sequence. An eleventh device generates parity check bits in response to every block of the final information-code-word sequence and a predetermined parity generation matrix of LDPC encoding. A twelfth device converts the parity check bits generated by the eleventh device into conversion code words respectively. Each of the conversion code words includes three bits among which two bits are “0” and one bit is “1”. A thirteenth device combines every block of the final information-code-word sequence and the related conversion code words generated by the twelfth device into an output-code-word sequence which obeys (1, k) RLL (run length limiting rules), where “k” is a predetermined natural number in the range of 9 to 12. The addition of the parity check bits to the information bit stream reduces the effective encoding rate.